User Contributed MET/CAL PROCEDURE ============================================================================= INSTRUMENT: HP 6633A:System DC Power Supply DATE: 28-Jan-97 AUTHOR: User Contributed REVISION: 0 ADJUSTMENT THRESHOLD: 70% NUMBER OF TESTS: 47 NUMBER OF LINES: 382 CONFIGURATION: Datron 1281 STANDARD: DTB Metered Variac STANDARD: EPC HS 5-500 ============================================================================= STEP FSC RANGE NOMINAL TOLERANCE MOD1 MOD2 3 4 CON 1.001 ASK+ X 1.002 ASK- R N P F W 1.003 HEAD ÍÍ INITIAL CONDITIONS ÍÍ 1.004 DISP The following Standard test equipment is needed: 1.004 DISP 1. Metered Variac (minimum of 10 amps) 1.004 DISP 2. EPC HS 5-500 5 Amp Shunt DTB # 14-107 1.005 DISP Connect the test equipment as follows: 1.005 DISP UUT AC line to variac. 1.005 DISP System IEEE port 1 to UUT IEEE connector. 1.006 STD DTB Metered Variac 1.007 DISP Adjust variac for an AC voltmeter reading of 115VAC. 1.008 DISP ÿ Connect the 1281 and the UUT as follows: 1.008 DISP ÿ [27][91]1m 1281 TO 6633A 1.008 DISP ÿ INPUT HI ÄÄÄÄÄÄÄÄÄ FRONT OUTPUT + 1.008 DISP ÿ INPUT LO ÄÄÄÄÄÄÄÄÄ FRONT OUTPUT - 1.009 DISP Set the UUT front panel controls as follows: 1.009 DISP LINE ....................... ON 1.010 HEAD {} 1.011 HEAD {ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»} 1.012 HEAD {º VOLTAGE PROGRAMING ACCURACY TEST º} 1.013 HEAD {ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ} 1.014 HEAD ÍÍ VOLTAGE PROGRAMING ACCURACY TEST ÍÍ 1.015 JMP 2.001 1.016 EVAL 2.001 IEEE CLR; 2.002 IEEE VSET 1; 2.003 IEEE OUT 1; 2.004 IEEE [@1281]DCV AUTO,FAST_ON 2.005 IEEE [@1281][D2000]RDG?[I] 2.006 ACC 2 1.000V 6P% 0.2P/ 2.007 MEME 2.008 MEMC V 0.05% 0.02U #! Test Tol 0.0205, Sys Tol 6.4e-006, TUR 3203.125 (>= 4.00). 3.001 IEEE VSET 2; 3.002 IEEE [@1281][D2000]RDG?[I] 3.003 ACC 20 2.000V 6P% 0.1P/ 3.004 MEME 3.005 MEMC V 0.05% 0.02U #! Test Tol 0.021, Sys Tol 1.4e-005, TUR 1500.000 (>= 4.00). 4.001 IEEE VSET 3; 4.002 IEEE [@1281][D2000]RDG?[I] 4.003 ACC 20 3.000V 6P% 0.1P/ 4.004 MEME 4.005 MEMC V 0.05% 0.02U #! Test Tol 0.0215, Sys Tol 2e-005, TUR 1075.000 (>= 4.00). 5.001 IEEE VSET 4; 5.002 IEEE [@1281][D2000]RDG?[I] 5.003 ACC 20 4.000V 6P% 0.1P/ 5.004 MEME 5.005 MEMC V 0.05% 0.02U #! Test Tol 0.022, Sys Tol 2.6e-005, TUR 846.154 (>= 4.00). 6.001 IEEE VSET 5; 6.002 IEEE [@1281][D2000]RDG?[I] 6.003 ACC 20 5.000V 6P% 0.1P/ 6.004 MEME 6.005 MEMC V 0.05% 0.02U #! Test Tol 0.0225, Sys Tol 3.2e-005, TUR 703.125 (>= 4.00). 7.001 IEEE VSET 6; 7.002 IEEE [@1281][D2000]RDG?[I] 7.003 ACC 20 6.000V 6P% 0.1P/ 7.004 MEME 7.005 MEMC V 0.05% 0.02U #! Test Tol 0.023, Sys Tol 3.8e-005, TUR 605.263 (>= 4.00). 8.001 IEEE VSET 7; 8.002 IEEE [@1281][D2000]RDG?[I] 8.003 ACC 20 7.000V 6P% 0.1P/ 8.004 MEME 8.005 MEMC V 0.05% 0.02U #! Test Tol 0.0235, Sys Tol 4.4e-005, TUR 534.091 (>= 4.00). 9.001 IEEE VSET 8; 9.002 IEEE [@1281][D2000]RDG?[I] 9.003 ACC 20 8.000V 6P% 0.1P/ 9.004 MEME 9.005 MEMC V 0.05% 0.02U #! Test Tol 0.024, Sys Tol 5e-005, TUR 480.000 (>= 4.00). 10.001 IEEE VSET 9; 10.002 IEEE [@1281][D2000]RDG?[I] 10.003 ACC 20 9.000V 6P% 0.1P/ 10.004 MEME 10.005 MEMC V 0.05% 0.02U #! Test Tol 0.0245, Sys Tol 5.6e-005, TUR 437.500 (>= 4.00). 11.001 IEEE VSET 10; 11.002 IEEE [@1281][D2000]RDG?[I] 11.003 ACC 20 10.000V 6P% 0.1P/ 11.004 MEME 11.005 MEMC V 0.05% 0.02U #! Test Tol 0.025, Sys Tol 6.2e-005, TUR 403.226 (>= 4.00). 12.001 IEEE VSET 20; 12.002 IEEE [@1281][D2000]RDG?[I] 12.003 ACC 200 20.000V 10P% 0.2P/ 12.004 MEME 12.005 MEMC V 0.05% 0.02U #! Test Tol 0.03, Sys Tol 0.00024, TUR 125.000 (>= 4.00). 13.001 IEEE VSET 30; 13.002 IEEE [@1281][D2000]RDG?[I] 13.003 ACC 200 30.000V 10P% 0.2P/ 13.004 MEME 13.005 MEMC V 0.05% 0.02U #! Test Tol 0.035, Sys Tol 0.00034, TUR 102.941 (>= 4.00). 14.001 IEEE VSET 40; 14.002 IEEE [@1281][D2000]RDG?[I] 14.003 ACC 200 40.000V 10P% 0.2P/ 14.004 MEME 14.005 MEMC V 0.05% 0.02U #! Test Tol 0.04, Sys Tol 0.00044, TUR 90.909 (>= 4.00). 15.001 IEEE VSET 50; 15.002 IEEE [@1281][D2000]RDG?[I] 15.003 ACC 200 50.000V 10P% 0.2P/ 15.004 MEME 15.005 MEMC V 0.05% 0.02U #! Test Tol 0.045, Sys Tol 0.00054, TUR 83.333 (>= 4.00). 16.001 HEAD {} 16.002 HEAD {} 16.003 HEAD {ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»} 16.004 HEAD {º VOLTAGE READBACK ACCURACY TEST º} 16.005 HEAD {ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ} 16.006 HEAD ÍÍ VOLTAGE READBACK ACCURACY TEST ÍÍ 16.007 JMP 17.001 16.008 EVAL 17.001 IEEE CLR; 17.002 IEEE VSET 1; 17.003 IEEE OUT 1;[D1000] 17.004 IEEE VOUT?;[I] 17.005 MEMC 1.000V 0.07% 0.030U #! T.U.R. not calculated because System Uncertainty not available. 18.001 IEEE VSET 2;[D1000] 18.002 IEEE VOUT?;[I] 18.003 MEMC 2.000V 0.07% 0.030U #! T.U.R. not calculated because System Uncertainty not available. 19.001 IEEE VSET 3;[D1000] 19.002 IEEE VOUT?;[I] 19.003 MEMC 3.000V 0.07% 0.030U #! T.U.R. not calculated because System Uncertainty not available. 20.001 IEEE VSET 4;[D1000] 20.002 IEEE VOUT?;[I] 20.003 MEMC 4.000V 0.07% 0.030U #! T.U.R. not calculated because System Uncertainty not available. 21.001 IEEE VSET 5;[D1000] 21.002 IEEE VOUT?;[I] 21.003 MEMC 5.000V 0.07% 0.030U #! T.U.R. not calculated because System Uncertainty not available. 22.001 IEEE VSET 6;[D1000] 22.002 IEEE VOUT?;[I] 22.003 MEMC 6.000V 0.07% 0.030U #! T.U.R. not calculated because System Uncertainty not available. 23.001 IEEE VSET 7;[D1000] 23.002 IEEE VOUT?;[I] 23.003 MEMC 7.000V 0.07% 0.030U #! T.U.R. not calculated because System Uncertainty not available. 24.001 IEEE VSET 8;[D1000] 24.002 IEEE VOUT?;[I] 24.003 MEMC 8.000V 0.07% 0.030U #! T.U.R. not calculated because System Uncertainty not available. 25.001 IEEE VSET 9;[D1000] 25.002 IEEE VOUT?;[I] 25.003 MEMC 9.000V 0.07% 0.030U #! T.U.R. not calculated because System Uncertainty not available. 26.001 IEEE VSET 10;[D1000] 26.002 IEEE VOUT?;[I] 26.003 MEMC 10.000V 0.07% 0.030U #! T.U.R. not calculated because System Uncertainty not available. 27.001 IEEE VSET 20;[D1000] 27.002 IEEE VOUT?;[I] 27.003 MEMC 20.000V 0.07% 0.030U #! T.U.R. not calculated because System Uncertainty not available. 28.001 IEEE VSET 30;[D1000] 28.002 IEEE VOUT?;[I] 28.003 MEMC 30.000V 0.07% 0.030U #! T.U.R. not calculated because System Uncertainty not available. 29.001 IEEE VSET 40;[D1000] 29.002 IEEE VOUT?;[I] 29.003 MEMC 40.000V 0.07% 0.030U #! T.U.R. not calculated because System Uncertainty not available. 30.001 IEEE VSET 50;[D1000] 30.002 IEEE VOUT?;[I] 30.003 MEMC 50.000V 0.07% 0.030U #! T.U.R. not calculated because System Uncertainty not available. 31.001 IEEE CLR; 31.002 DISP Set the UUT front panel controls as follows: 31.002 DISP LINE ....................... OFF 31.003 HEAD {} 31.004 HEAD {} 31.005 HEAD {ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»} 31.006 HEAD {º CURRENT PROGRAMMING VERIFICATION TEST º} 31.007 HEAD {ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ} 31.008 HEAD ÍÍ CURRENT PROGRAMMING VERIFICATION TEST ÍÍ 31.009 STD EPC HS 5-500 31.010 JMP 32.001 31.011 EVAL 32.001 DISP ÿ Connect the HS 5-500 and the UUT as follows: 32.001 DISP ÿ [27][91]1m HS 5-500 TO 6633A 32.001 DISP ÿ INPUT HI ÄÄÄÄÄÄÄÄÄ OUTPUT + 32.001 DISP ÿ INPUT LO ÄÄÄÄÄÄÄÄÄ OUTPUT - 32.002 DISP ÿ Connect the HS 5-500 and the 1281 as follows: 32.002 DISP ÿ [27][91]1m HS 5-500 TO 1281 32.002 DISP ÿ SENSE TERMINAL HI ÄÄÄÄÄÄÄÄÄ INPUT HI 32.002 DISP ÿ SENSE TERMINAL LO ÄÄÄÄÄÄÄÄÄ INPUT LO 32.003 DISP Set the UUT front panel controls as follows: 32.003 DISP LINE ....................... ON 32.004 MEMI Use keyboard to enter 2 amp shunt resistance in ohms: 32.005 MEME 32.006 MATH M[1] = MEM1 32.007 IEEE VSET 10; 32.008 IEEE ISET .1;[D1000] 32.009 IEEE OUT 1; 32.010 IEEE [@1281][D2000]RDG?[I] 32.011 MATH MEM = MEM / M[1] #32.011 ACC 2 0.1000V 6P% 0.2P/ 32.012 MATH MEM1 = 0.1 32.013 MEME 32.014 MEMC A 0.15% 0.0020U #! Test Tol 0.00215, Sys Tol 1.4e-005, TUR 153.571 (>= 4.00). 33.001 IEEE ISET .5;[D1000] 33.002 IEEE [@1281][D2000]RDG?[I] 33.003 MATH MEM = MEM / M[1] #33.004 ACC 2 .50000V 6P% 0.2P/ 33.004 MATH MEM1 = .5 33.005 MEME 33.006 MEMC A 0.15% 0.0020U #! Test Tol 0.00275, Sys Tol 0.00014, TUR 19.643 (>= 4.00). 34.001 IEEE ISET 1;[D1000] 34.002 IEEE [@1281][D2000]RDG?[I] 34.003 MATH MEM = MEM / M[1] #33.004 ACC 2 1.00000V 6P% 0.2P/ 34.004 MATH MEM1 = 1 34.005 MEME 34.006 MEMC A 0.15% 0.0020U #! Test Tol 0.0035, Sys Tol 0.00024, TUR 14.583 (>= 4.00). 35.001 IEEE ISET 1.5;[D1000] 35.002 IEEE [@1281][D2000]RDG?[I] 35.003 MATH MEM = MEM / M[1] #33.004 ACC 2 1.50000V 6P% 0.2P/ 35.004 MATH MEM1 = 1.5 35.005 MEME 35.006 MEMC A 0.15% 0.0020U #! Test Tol 0.00425, Sys Tol 0.00034, TUR 12.500 (>= 4.00). 36.001 JMP 37.001 36.002 IEEE ISET 1.6;[D1000] 36.002 IEEE ISET 1.7;[D1000] 36.002 IEEE ISET 1.8;[D1000] 36.002 IEEE ISET 1.9;[D1000] 36.002 IEEE ISET 1.99;[D1000] 36.002 IEEE ISET 2;[D1000] 36.003 IEEE [@1281][D2000]RDG?[I] 36.004 MATH MEM = MEM / M[1] #33.004 ACC 2 2.00000V 6P% 0.2P/ 36.005 MATH MEM1 = 2 36.006 MEME 36.007 MEMC A 0.15% 0.0020U #! Test Tol 0.005, Sys Tol 0.00044, TUR 11.364 (>= 4.00). 37.001 IEEE CLR; 37.002 HEAD {} 37.003 HEAD {} 37.004 HEAD {ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»} 37.005 HEAD {º CURRENT READBACK ACCURACY TEST º} 37.006 HEAD {ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ} 37.007 HEAD ÍÍ CURRENT READBACK ACCURACY ÍÍ 37.008 JMP 38.001 37.009 EVAL 38.001 IEEE VSET 2; 38.002 IEEE OUT 1; 38.003 IEEE ISET .5;[D1000] 38.004 IEEE IOUT?;[I] 38.005 MEMC .5000A 0.18% 0.009U #! T.U.R. not calculated because System Uncertainty not available. 39.001 IEEE ISET 1;[D1000] 39.002 IEEE IOUT?;[I] 39.003 MEMC 1.0000A 0.18% 0.009U #! T.U.R. not calculated because System Uncertainty not available. 40.001 IEEE ISET 1.5;[D1000] 40.002 IEEE IOUT?;[I] 40.003 MEMC 1.5000A 0.18% 0.009U #! T.U.R. not calculated because System Uncertainty not available. 41.001 IEEE CLR; 41.002 DISP Set the UUT front panel controls as follows: 41.002 DISP LINE ....................... OFF 41.003 HEAD {} 41.004 HEAD {ÍÍ RIPPLE AND NOISE TEST ÍÍ} 41.005 JMP 42.001 41.006 EVAL 42.001 DISP Remove the jumpers from the UUT OUTPUT +S, S and -S, S 42.001 DISP terminals. 42.002 DISP ÿ Connect the DLP 50 and the UUT as follows: 42.002 DISP ÿ [27][91]1m DLP 50 TO 6633A 42.002 DISP ÿ INPUT HI ÄÄÄÄÄÄÄÄÄ REAR OUTPUT + 42.002 DISP ÿ INPUT LO ÄÄÄÄÄÄÄÄÄ REAR OUTPUT - 42.002 DISP ÿ INPUT HI ÄÄÄÄÄÄÄÄÄ REAR OUTPUT +S 42.002 DISP ÿ INPUT LO ÄÄÄÄÄÄÄÄÄ REAR OUTPUT -S 42.003 DISP ÿ Connect the UUT and the 1281 as follows: 42.003 DISP ÿ [27][91]1m 6633A TO 1281 42.003 DISP ÿ OUTPUT +S ÄÄÄÄÄÄÄÄÄ INPUT HI 42.003 DISP ÿ OUTPUT -S ÄÄÄÄÄÄÄÄÄ INPUT LO 42.004 DISP Set the UUT front panel controls as follows: 42.004 DISP LINE ....................... ON 42.005 DISP Set the DLP 50 front panel controls as follows: 42.005 DISP VOLTS RANGE ........................................ 60V 42.005 DISP AMPS RANGE ......................................... 18A 42.005 DISP MODE ............................................. 0-30A 42.005 DISP DC switch .......................................... OFF 42.005 DISP LOAD ADJUST COARSE/FINE ...................... fully ccw 42.006 IEEE VSET 50; 42.007 IEEE ISET 2; 42.008 IEEE OUT 1; 42.009 DISP Set the DLP 50 front panel controls as follows: 42.009 DISP DC switch ........................................... ON 42.010 DISP Adjust DLP 50 COARSE and FINE LOAD ADJUST controls 42.010 DISP for a UUT reading of 2 amps. 42.010 DISP 42.010 DISP NOTE: Be careful not to exceed 2 amps or UUT will 42.010 DISP cross-over into constant current mode. If this occurs, 42.010 DISP go to local mode and make necessary corrections 42.010 DISP manually. 42.011 DISP NOTE: It may be necessary to temporarily power off 42.011 DISP the system monitor durring this portion of the test if 42.011 DISP failures occur. 42.012 DISP Adjust variac for an reading of 115VAC. 42.013 IEEE [@1281] ACV AUTO 42.014 IEEE [@1281] [D5000]RDG?[I] 42.015 MEM* 1000 42.016 ACC 200 0.000mVRMS 200P% 20P/ 42.017 MEME 42.018 MEMC mVRMS 0.500U 60H #! Test Tol 0.5, Sys Tol 0.004, TUR 125.000 (>= 4.00). 43.001 HEAD {} 43.002 HEAD {ÍÍ LINE REGULATION TEST ÍÍ} 43.003 JMP 44.001 43.004 EVAL 44.001 DISP Adjust variac for an reading of 104VAC. 44.002 IEEE [@1281] DCV AUTO,FAST_ON 44.003 IEEE [@1281] [D2000]RDG?[I] 44.004 MEME 44.005 DISP Adjust variac for an reading of 127VAC. 44.006 IEEE [@1281] [D2000]RDG?[I] 44.007 MEM- 44.008 MEM* 1000 44.009 ACC 200 0.000mV 7P% 0.5P/ 44.010 MEME 44.011 MEMC mV 1.000U #! Test Tol 1, Sys Tol 0.0001, TUR 10000.000 (>= 4.00). 45.001 DISP Adjust variac for an reading of 115VAC. 45.002 HEAD {} 45.003 HEAD {ÍÍ LOAD REGULATION TEST ÍÍ} 45.004 JMP 46.002 45.005 EVAL 46.001 DISP Set the DLP 50 front panel controls as follows: 46.001 DISP DC switch ........................................... ON 46.002 IEEE [@1281] [D2000]RDG?[I] 46.003 MEME 46.004 DISP Set the DLP 50 front panel controls as follows: 46.004 DISP DC switch .......................................... OFF 46.005 IEEE [@1281] [D2000]RDG?[I] 46.006 MEM- 46.007 MEM* 1000 46.008 ACC 200 0.000mV 7P% 0.5P/ 46.009 MEME 46.010 MEMC mV 4.000U #! Test Tol 4, Sys Tol 0.0001, TUR 40000.000 (>= 4.00). 47.001 IEEE CLR; 47.002 HEAD {} 47.003 DISP {ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»} 47.003 DISP {º THIS COMPLETES THE VERIFICATION º} 47.003 DISP {ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ} 47.004 END #! T.U.R.s less than 4.00: 0 #! T.U.R.s estimated using RANGE value: 0 #! T.U.R.s not calculated (ASK- U): 0 #! T.U.R.s not computable at compile time: 17 #! FOR JUSTIFICATION REFER TO COMMENTS FOLLOWING EACH TEST IN THIS LISTING.